The present invention relates, in general, to the field of testing the functionality of integrated circuit memory devices. More particularly, the present invention relates to a test interface of particular applicability in verifying the functionality of high speed embedded memories such as synchronous dynamic random access memories (xe2x80x9cSDRAMxe2x80x9d).
At present, the testing of high speed integrated circuit memory devices, particularly embedded memories, requires the use of similarly high speed capable testers. This then precludes the use of existing, relatively slower speed test environments while the higher speed test equipment becomes increasingly expensive to produce and purchase. Moreover, the higher device speed testing capability of even state-of-the-art test equipment is nevertheless still limited by the bandwidth of the physical interface connections and bussing to the device under test.
Since embedded memory macros generally interface only to other on-chip circuitry, the operating speeds of such memory arrays are generally significantly faster than that of commodity dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) components that instead connect to off-chip circuitry and interface busses. Typically, embedded memories operate at frequencies several times faster than non-embedded memories. Further, embedded memory arrays usually have extremely wide input/output (xe2x80x9cI/Oxe2x80x9d) configurations (e.g. typically 128 to 256 bits wide) which also adds to the already high degree of difficulty in the high speed testing of these memories.
The high speed test interface for embedded memories particularly disclosed herein advantageously allows for the utilization of existing, relatively low speed, (and hence low cost), testers to test high speed memory macros or other embedded memory including SDRAM. The present invention specifically provides a on-chip test interface and method for verification of an embedded memory macro design that can use these relatively low-cost memory testers. This is effectuated by means of a test interface for providing access to an embedded memory macro with separate on-chip test circuitry so that half-rate, narrow word, input signals from the tester can perform all memory macro operations across the breadth of the wide I/O architecture. The on-chip test circuitry may include a synchronizing circuit in order to minimize skew between the external clock and the data output from the test chip.
In the particular implementation of the present invention disclosed herein, a monolithically integrated xe2x80x9chard-wiredxe2x80x9d and constantly enabled interface is provided between an embedded memory macro and the external off-chip tester. The external clock inputs can then operate at half the frequency of the on-chip clock. This is effectuated by using a clock frequency doubler in the test chip interface circuitry (integrated on-chip) that accepts two differential clocks (e.g. CLK0, CLK0B, CLK1 and CLK1B) where the CLK1 signal is delayed from the CLK0 signal clock by 90 degrees. The present invention further incorporates the technique of latching data from input pad-pair sources to one or more 2-to-1 multiplexer(s) that use the internal frequency doubled clock signals to switch the multiplexer(s) for generation of data as an input to the embedded DRAM macro at twice the rate of the externally applied data. This data-in acceleration is also used for input data masking (for data mask bits that operate at the same rate as the data in).
In a particular implementation of the present invention, sixteen data inputs are used by eight data-in accelerators where the output of each data-in accelerator is connected in parallel to the data inputs of four byes of the memory macro. In this way, sixteen external data inputs can be used to write eight groups of four bytes (32 bits) of inputs resulting in all 256 data inputs being written to an externally determined data state. In a xe2x80x9creadxe2x80x9d operation from the 256 bit wide I/O bus, data multiplexing is carried out such that a multiplexer signal selects one-of-thirty two outputs within a four byte field to be read from one of the output data pins.
The multiplexer may be split into two levels with multiplexing selection being carried out as a one-of eight operation, followed by a one-of-four. Through the use of the technique disclosed herein, a data rate reduction is implemented wherein either xe2x80x9cevenxe2x80x9d data or xe2x80x9coddxe2x80x9d data is sent to the data output pins of the test chip. xe2x80x9cEvenxe2x80x9d or xe2x80x9coddxe2x80x9d data is selected by means of another multiplexer signal which, in a representative embodiment, determines if the synchronizer captures and aligns xe2x80x9cevenxe2x80x9d or xe2x80x9coddxe2x80x9d data. In this manner, the synchronizer performs two tasks, to wit, xe2x80x9cevenxe2x80x9d/xe2x80x9coddxe2x80x9d data selection and realignment of the output data to the system clock to xe2x80x9cde-skewxe2x80x9d the output data.